Generally, a semiconductor chip, or integrated circuit, is mounted on a printed circuit board or the like and the accepted method for connecting the chip to external circuits is to use standard wire bond technology. However, when a semiconductor chip having a relatively large array of electrical components or devices formed thereon is to be connected, standard wire bond techniques can become very difficult. For example, if a relatively large array (greater than, for example, 10,000 or 100.times.100) of light emitting diodes is formed on a semiconductor chip with a pitch (center-to-center separation) of P, then bond pads on the perimeter of the semiconductor chip will have a 2P pitch. This is true because every other row and every other column goes to an opposite edge of the perimeter to increase the distance between bond pads as much as possible.
At the present time wire bond interconnects from bond pads having a pitch of 4.8 milli-inches is the best that is feasible. Thus, in the array mentioned above of 100.times.100 light emitting diodes the bond pads on the perimeter of the semiconductor chip would have a minimum pitch of 4.8 milli-inches, with 50 bond pads situated along each edge of the perimeter. As more devices are included in the array, more bond pads are required and the perimeter size to accommodate the additional bond pads increases at an even greater rate. That is, since the minimum pitch of the bonding pads is 4.8 milli-inches, the pitch of the devices in the array can be as large as 2.4 milli-inches, or approximately 61 microns, without effecting the size of the chip. Thus, even if the devices can be fabricated smaller than 61 microns, the minimum pitch of the bonding pads will not allow the perimeter of the chip to be made any smaller. It can quickly be seen that the size of the semiconductor chip is severely limited by the limitations of the wire bonding technology.
Further, it has been common practice to mount semiconductor chips and interface circuitry on a single board. The problem that arises is the large amount of surface area required to mount and connect various components.
Thus, there is a need for interconnect and packaging structures and techniques which can substantially reduce the limitation on size of semiconductor chips and which can reduce the amount of required surface area.
Accordingly, it is a purpose of the present invention to provide integrated electro-optical packages which are not limited in size by the electrical connections.
It is another purpose of the present invention to provide integrated electro-optical packages which are substantially smaller than previous integrated packages.
It is still another purpose of the present invention to provide integrated electro-optical packages which contain substantially greater numbers of light generating devices than previous integrated packages.
It is yet another purpose of the present invention to provide integrated electro-optical packages which contain arrays of light generating devices with substantially greater numbers of devices than previous integrated packages.